This invention relates to electronic circuits and more specifically to bus controllers.
The Personal Computer (PC) industry is migrating towards power management architectures such as the Advanced Configuration and Power Interface described in the Advanced Configuration and Power Interface Specification, Revision 1.0 and dated Dec. 22, 1996, that specify low power requirements for the components in a PC. The Advanced Configuration and Power Interface Specification (ACPI Spec.) is incorporated herein by reference. Currently, peripheral bus controllers (for example, a Universal Serial Bus Host Controller) remain clocked (and therefore powered up) in order to meet their timing specifications. As a result, requirements for low power modes are not generally called for in bus controller specifications.
The Universal Serial Bus (USB) architecture has become the de facto standard in the PC industry for interfacing peripheral devices (for example, mouse, keyboard, printer, etc.) with a central processing unit (CPU) of a host computer. The requirements for the USB architecture are detailed in the Universal Serial Bus Specification (USB Spec) which is herein incorporated by reference. The USB Host Controller (Host) is the interface between a peripheral device and the host computer. USB Devices connect to the bus through a USB Port.
A USB Hub is a USB Device that provides additional port connections to the USB. A USB Hub is somewhat unique in that it allows responses to actions on a Port in accordance with the USB Spec. This generally requires that the USB Hub provide some of the same functionality as a USB Host.
Current implementations of the USB Host maintain the controlling clock signal active even when other USB devices are set in a low power state. The active clock signal causes the USB Host to continue to draw power during a low power state. The controlling clock signal is maintained in an active state because signals may be generated on the USB during the low power state. For example, disconnecting a USB device generates a Single Ended Zero (SE0) signal on the USB and connecting a device generates a CONNECT signal on the USB. In addition, activating one of the USB Devices (for example, pressing a keyboard button) generates an upstream (towards the host computer) RESUME signal on the USB. The USB Spec requires a fast response to a RESUME signal. For example, a downstream (away from the host computer) response to the receipt of a RESUME signal must be generated in less than fifty microseconds (xcexcs) according to the current version of the USB Spec. An SE0 or CONNECT does not require a signal to be sent within this short time period to the USB Device but the system must be notified and the host computer made aware that a USB device has either been connected or disconnected. Signals from the USB device may then be processed normally.
As described above, a USB Host or Hub remains clocked so that it can receive and respond to either a RESUME, CONNECT, or SE0 signal from a USB Device within the time specified by the USB Spec. Typically, this means that the circuit continuously draws full power. In applications such as portable notebook and laptop computers, the ability to conserve power is critical in extending the duration the device can function on a battery supply or to lower total system power. As a result, the computer industry strives to reduce the power consumption of components when the computer is in a low power mode. It has been difficult, however, to place a USB Host or Hub in a low power mode and retain full USB functionality. A further problem is that transitions from an IDLE state to a RESUME state may be momentarily misinterpreted as an SE0 signal.
The present invention provides an asynchronous logic circuit that suspends the clock in a bus controller and places the device in low power mode. The asynchronous logic circuit functions as an event detector and responder not requiring clocks. While in low power mode, bus events can be detected and reported to the bus controller after wake up is complete. Additionally, the asynchronous logic circuit can respond to bus events until the bus controller is fully powered and ready to take over control.